The present invention relates to a semiconductor memory device, and more particularly, to a dynamic random-access memory using metal oxide semiconductor field-effect transistors (MOSFETs).
In the recent years, dynamic random-access memories (hereinafter referred to as "dRAMs") have been improved to have a greater memory capacity and to operate at a higher speed. In order to provide this memory capacity, a micro-fabrication technique is required to make the memory cells as small as possible. Now, dRAMs are being developed in which the transistors used as memory cells have a "submicron" size and which, therefore, have an extremely high integration density. Each of these dRAMs includes a sense amplifier for sensing the level difference between the signal read from a memory cell and the signal read from a dummy cell. The sense amplifier is also composed of MOSFETs having a submicron size. More specifically, these micro-fabricated MOSFETs have a gate length of 0.5 micrometers or less. The shorter the gate length, the more intense the inner electric field of a MOSFET. Hence, the bias voltage for the MOSFET must be lowered to render the MOSFET sufficiently reliable. This is because, when the inner electric field of the MOSFET becomes intense, over-coming the source-drain withstand voltage which is specific to transistors made of a particular material, the probability of malfunction or the probability of breakdown greatly rises. However, when the bias voltage is lowered, the switching speed of the MOSFET is proportionally reduced, thus decreasing the data-reading speed of the dRAM. Therefore, it would be difficult to provide a great-capacity, high-speed dRAM even if the size of the memory cells were simply reduced to the submicron order.
In order to make a dRAM operate at high speed, bipolar transistors can be used for memory cells. Bipolar transistors have, by nature, a great current driving ability. A dRAM whose memory cells use bipolar transistors is able to operate at high speed. As is well known in the art, however, bipolar transistors cannot be micro-fabricated, and can scarcely serve to provide a memory with a great memory capacity. Consequently, it would also be difficult to provide a great-capacity, and yet high-speed dRAM when bipolar transistors were used for memory cells.
The present invention further relates to dynamic random access memory devices, and more particularly to dynamic random access memory devices performing high speed and high integration with bit-line sense amplifiers comprising MOS transistors and Bipolar transistors.
As discussed above, the degree of integration of dynamic random access memories (DRAM) has been advancing with an advancement of micro-fabrication techniques. In conjunction with this, the efficiency of the elements has improved, and thereby the access time of the DRAMs has become shorter.
However, when the gate length is decreased to about 0.5 .mu.m or below, it will be necessary to reduce the supply voltage in order to maintain reliability of the elements. Therefore, it will become more difficult to achieve higher speeds.
A proposal was made to introduce bipolar transistors as a part of the DRAM because they have a larger current carrying ability compared to MOS transistors, and therefore can achieve higher speeds. For example, a differential amplifier has been suggested including bipolar transistors as its drivers. Such a circuit configuration incorporating bipolar transistors into a MOS circuit is called a BIMOS circuit. However, the area dominated with BIMOS sense amplifier becomes large as compared with one constructed only by MOS transistors. Therefore, a design in which one BIMOS sense amplifier is connected to a plurality of bit-line pairs is preferable. (Japanese Patent Disclosure (Kokai) No. 61-142594)
DRAM memory cells consist of one transistor/one capacitor, and need re-writing or restoring after reading out, because the DRAM uses a destructive type read out. Conventionally, the restoring was carried out together with the information sensing of the memory cells, using a CMOS flip-flop as a bit-line sense amplifier. In order to read out the information of the memory cells at high speed, it is preferable to activate the BIMOS sense amplifier before activating this CMOS flip-flop. However, if the bit-line directly connects to the base of the bipolar transistor, which is the driver of the BIMOS sense amplifier, the information in the memory cell is destroyed. This is because the signal charge in the memory cell transferred to the bit line is used as a base current. Thereby, a buffer circuit with high input impedance is disposed between the BIMOS differential amplifier and a bit-line pair.